МИКРОЭЛЕКТРОНИКА, 2011, том 40, № 2, с. 154-158
-- СХЕМОТЕХНИКА :
УДК 621.382
SUBTHRESHOLD SCHMITT TRIGGER USING BODY-BIAS TECHNIQUE FOR ULTRA LOW POWER AND HIGH PERFORMANCE APPLICATIONS
© 2010 Vandana Niranjan*, Maneesha Gupta**, Chanchal*
* Indira Gandhi Institute of Technology, Deptt. of Electronics and Communication Engineering, Kashmere Gate, Delhi, INDIA ** Netaji Subhash Institute of Technology Deptt. of Electronics and Communication Engineering, Dwarka, Delhi, INDIA
E-mail: Vandana7379@gmail.com Received May 9, 2010
Digital subthreshold logic provides extremely low power consumption since the power supplies are kept below the threshold voltage and using the small subthreshold current of MOS transistors to operate. In this paper, a body-bias technique to match the subthreshold currents of both the NMOS and PMOS transistors is explored and a Schmitt trigger circuit employing this bias technique is proposed. Extensive circuit simulations were conducted and the results were compared with standard body bias technique in terms of performance parameters. The simulation results were obtained with 0.18 p.m technology parameters. The conclusion is that Schmitt trigger with this body biasing is suitable for high performance and ultra low power applications.
I. INTRODUCTION
Body biasing techniques control the voltage of body of MOSFET to control and reduce leakage power. In
body biasing techniques basically VSB is modulated to change VT as can be seen from (1) which shows various parameters that affect the threshold voltage of a MOS transistor.
Vt = Vto
+
У(л/ 12ФFl + Vsb - Л2Ф?| ) - nVDS
(1)
where VT0 is the zero body bias threshold voltage and mainly depends on the manufacturing process. y is the body effect coefficient (typically equals to 0.4 V05) and it depends on the gate oxide capacitance, silicon permittivity, doping level and other parameters. Of is the surface potential at threshold (typically |—2^pF| equals 0.6 V). VSB is the source-to-body voltage. The term nVDS represent the effect ofDrain-Induced Barrier Lowering (D1BL) in
which n is the D1BL coefficient and it is in the range of 0.02-0.1.
Subthreshold logic dissipates less power since the power supply Vdd is kept less than the threshold voltage VT to ensure operation in the subthreshold region and the fact that the circuit uses the small subthreshold (or leakage) current ofMOS transistors. Since the subthreshold current depends exponentially on the gate voltage, we expect an exponential increase in delay [1-3]. The subthreshold current of the N(P)MOS transistor is given by (2).
Idn(p) - Iqn(p)exP((—)
vgb - vt n( p ) - nn( p ) vsb
n
n( p)y T
1 - exp \ -(+)
V
ds
(2)
Where lo is a scaling current, proportional to mobility, oxide capacitance per unit area and aspect ratio W/L, n is the slope factor, VT is MOSFET threshold voltage, VGB is gate voltage w.r.t body or substrate, VSB is source voltage w.r.t body and VDS is drain voltage w.r.t body. Expression (2) also shows that the variation of the source-to-body voltage VSB of the transistor affects the drain current. With a proper source-to-substrate voltage the same drive current in the NMOS and PMOS transistors can be achieved. In this paper a body-bias technique to match
the subthreshold currents of both the NMOS and PMOS transistors is explored and a Schmitt trigger employing this bias technique is proposed. By simulation it is shown that the Schmitt trigger with this body biasing is suitable for high performance and low power applications.
The remainder of the paper proceeds as follows. In section II we present the bias circuit to generate body bias voltage Vw for matching the subthreshold currents of the NMOS and PMOS transistors. We also present simula-
SUBTHRESHOLD SCHMITT TRIGGER USING BODY-BIAS TECHNIQUE 155
Vdd Vdd
Vin
-Vo,
-Vw
Fig. 1. CMOS inverter with standard body bias.
Fig. 2. Biasing circuit.
tion results of CMOS inverter biased with Vw. In section 111 simulation has been performed on individual logic circuits, namely the Inverter, NAND gate, NOR gate and MUX based latch using proposed body biasing technique and then compared with standard body bias version of these logic circuits. In section IV a Schmitt trigger circuit is simulated with proposed body biasing technique for speed and power performance. Conclusions are summarized in section V
II. BIAS VOLTAGE GENERATION CIRCUIT
In a CMOS inverter with standard body bias, body of NMOS transistor is connected to ground and that of PMOS transistor is connected to Vdd as shown in Fig. 1.
For a given power supply, the drive currents of the PMOS and NMOS transistors in subthreshold are different by an order of magnitude. As a consequence the rise and fall times will also differ by an order of magnitude. The result is a waste of energy due to the higher current since the switching frequency is mostly determined by the higher of the rise and the fail times. A biasing circuit to provide an appropriate body-bias voltage Vw proposed in [7] as shown in Fig. 2.
The voltage Vw in Fig. 2 stabilizes at a value such that the current of the PMOS and NMOS devices are the same for an input equal to the gate threshold voltage Vr. Considering both NMOS and PMOS in saturation, the analysis of Fig.2 using (2) yields following equation
Vw = VT =
vdd + vtn
2 2nN
|vtp| + ( 1qp
2nP
i
i on'
(3)
The bias circuit in Fig. 2 is used to bias the bodies of that in Fig. 5 and hence rise time and fall times will also
NMOS and PMOS transistors in inverter as shown in Fig.3.
Inverter is simulated for Vdd of 0.5V and the waveforms for voltage levels of nodes D, Q, and VW are shown in Fig. 4.
We observe that Vw is maintained at a value around 200 mV while there is no switching at the input D. It pulsates to approximately 100 mV or 300 mV at D's low-to-high or high-to-low transitions accordingly. When D switched from low to high, the lowering of Vw reduced the threshold voltage of NMOS and increased threshold voltage of PMOS as a result of body effect. This in turn facilitated the pull-down operation and reduced the D-to-Q delay. Vise versa, when D switched from high to low, the higher Vw resulted in an improved low-to-high switching of Q. The driving current of transistors in the inverter with standard body bias is shown in Fig. 5 and that with proposed body bias is shown in Fig. 6. It can be observed that by biasing the bodies of transistors at V^, the drive currents are equalized in Fig. 6 as compared to
become almost same.
For a CMOS inverter, the driving currents in the transistors with body bias and with standard bias are as com-
V
dd
D-
Vw
—Q
-Vw
Fig. 3. Inverter with proposed body-bias technique.
156
VANDANA NIRANJAN h gp.
/Q
(V) 500m r /D
250m -
0m (V) 500m 250m 0m (V) 300m 200m 100m
0m
Transient Response
r
0n 100n 200n 300n 400n
Time, s
Fig. 4. Transient response of body biased inverter.
V
dd
Vin
V
out
V
dd
w
A Transient Response
1.40u r O:/M9/D p
1.10u 800n 500n 200n
— 100n
0 100n 200n 300n 400n
Time, s
Fig. 5. Drive currents in transistors with standart body-biased Inverter.
A Transient Response
1.10ur°:/M9/D p
800n 500n 200n
— 100n
0
100n
200n
300n
400n Time, s
Fig. 6. Drive currents in transistors with proposed body biased Inverter.
pared in Fig.5. By biasing the bodies of transistors at Vw. the currents are equalized and rise and fall times are almost the same compared to standard bias value.
Fig. 7. Schmitt trigger circuit.
III. LOGIC GATES WITH PROPOSED BODY BIAS TECHNIQUE
Simulation has been performed on individual logic circuits, namely the inverter, NAND gate, NOR gate and MUX based latch for standard body bias and proposed body bias at Vdd =0.5 V [4—6]. The speed and power performance parameters of inverter, NAND, NOR, and MUX-based latch are summarized in Table 1(a—d).
In general, by biasing the transistor bulks at Vw, the delay as well as the difference between rise and fall times was favorably reduced. Although the power consumption is higher with body bias, it is still considered to be ultra-low power compared to circuits operating at strong inversion.
IV SCHM1TT TRIGGER CIRCUIT USING PROPOSED BODY BIAS TECHNIQUE
A novel Schmitt trigger circuit is shown in Fig. 7 [8, 9]. The performance of the Schmitt trigger was evaluated by employing proposed body bias and was compared with standard body bias. To simulate a load capacitance CL was set to 18fF. An ideal saw waveform was used as input signal whose voltage is 0.5 V Figure 8(a) shows the DC VTC of the circuit with proposed body bias approach and figure 8(b) shows the input waveform and output waveform.
Table 2 summarizes the power and performance comparison results of Schmitt trigger with standard body bias and proposed body bias. In general, Schmitt trigger circuit implemented with proposed body-bias provides better speed performance with moderate power consump-
МHКРОЭ.ПЕКTРОНHКA tom 40 № 2 2011
SUBTHRESHOLD SCHMITT TRIGGER USING BODY-BIAS TECHNIQUE
157
Table 1(a)
(a)
Table 1(d)
Table 2
Inverter DELAY (ps) POWER
Rising Falling Average
Standard Body bias Proposed Body-bias 2285 855 570 450 1428 653 975 pW 7.65 nW
Table 1(b)
Nand Gate DELAY (ns) POWER (nW)
Rising Falling Average
Standard Body bias Proposed Body-bias 3.13 1.03 0.957 0.669 2.03 0.848 1.71 8.93
Table 1(c)
NOR Gate DELAY (ns) POWER (nW)
Rising Falling Average
Standard Body bias Proposed Body-bias 6.12 0.959 0.625 0.509 3.36 0.725 1.62 27.6
Latch DELAY (ns) POWER
Rising Falling Average (nW)
Standard Body bias 3.65 5.13 4.39 1.22
Proposed Body-bias 1.03 1.75 1.37 7.93
Vdd-0.5 V Schmitt trigger with Standard Body bias Schmitt trigger with Proposed Body-bias
Dynamic Power dissipation (nW) 142.3 162.7
Static Power dissipation (pW) 6.3 7.4
Propagation delay (psec) 175.3 132.8
Fig. 8 (a). DC Voltage transfer characteristics of Schmitt trigger with proposed body bias. (b). Input and output wavefor
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